A conventional tristate output buffer circuit transmits binary data signals of high and low potential levels from an input node to an output node. The high and low potentials represent two of the three states of the output buffer circuit. Typically a tristate output buffer establishes a high impedance at the output pad for the third state.
FIG. 1 is a typical timing diagram of a serial access memory of the related art. During time periods 5 serial data, voltage out high, v.sub.OH, and voltage out low, v.sub.OL, is driven to the output pad. It can be seen from the timing diagram that there is a undefined time period 10 existing between the clocking of each bit of serial data to the output pad. The potential of the output pad during the undefined period 10 has a "don't care" condition.
It can be seen from the timing diagram that the serial data may transition from a v.sub.OL to a v.sub.OH or from a v.sub.OH to a v.sub.OL. The length of time required for a node to transition from one potential to another is directly proportional to the change in voltage, delta V, between the two potentials. There is also an overshoot of the potential in the case where the potential transitions from a low to a high potential. The overshoot is defined as the potential difference between the maximum potential to which the node is driven and the desired potential being driven to the node. Similarly, in a transition from a high potential to a low potential undershoot occurs. In both cases there is ringing as the potential damps to the desired potential. Ringing occurs when the potential at the node fluctuates near the desired value until settling at the desired value. Overshoot, undershoot and ringing decrease the speed and integrity of the memory device. FIG. 2 is a timing representation of a simulation depicting the voltage 15 at the output pad and the voltage of a clock signal 20 of a circuit of the related art. The circuit is typified as having overshoot 25, undershoot 30 and ringing 35.
FIG. 3 is a simplified depiction of an output buffer 40 of the related art. A control circuit 45 provides the signals that actuate the output buffer 40. A high on the gate of transistor 50 drives the potential of the output pad 53 to a high logic level of a supply potential, V.sub.cc, through transistor 50. A high on the gate of transistor 55 drives the potential of the output pad 53 to a low logic level of a reference potential at reference node 56 through transistor 55. When the gates of both transistors are at a low potential both transistors 50 and 55 are deactuated and high impedance is seen at the output pad 53. Although a high impedance appears at the output pad 53 the potentials initially driven to the output pad 53 have not dissipated appreciably. Therefore in order to drive the next bit of serial data to the output pad 53 the potential on the output pad 53 may have to transition between the extremes of the two logic levels. This large change in voltage creates overshoot and undershoot of the output signal and the subsequent ringing of the output signal before the desired logic level is driven to the output pad. Overshoot, undershoot, and ringing can decrease the speed of the memory device, negate normal noise margins, and cause damage to other parts connected to the bus.
In order to increase speed it is also desirable to eliminate crossing current. Crossing current represents a current surge which flows between power rails through the output buffer. It typically results from momentary, simultaneous activation of two series connected active devices located between the power rails. These current surges are undesirable because they cause excess power consumption and because they produce voltage degradation on the power and ground busses within the device. This voltage degradation can decrease device speed. For example, if transistor 50 actuates to drive the output pad 53 to a high logic level and transistor 55 does not turn off immediately there will be current flow through transistor 55 as well as transistor 50. By eliminating crossing current only one transistor will conduct current at any given time.
Pages 5-111 through 5-154 of the 1992 DRAM DATA BOOK by Micron Technology, Inc. and U.S. Pat. No. 4,953,130, by Theodore W. Houston, entitled MEMORY CIRCUIT WITH EXTENDED VALID DATA OUTPUT TIME are herein incorporated by reference to provide the reader with further information.